Task #11778
Feature #11648: Simulation d'un circuit de détection de défauts sous PSIM
Terminer montage et simulation
| Status: | Closed | Start date: | 10/23/2019 | |
|---|---|---|---|---|
| Priority: | Normal | Due date: | ||
| Assignee: | Haosheng ZHANG | % Done: | 0% | |
| Category: | - | Estimated time: | 4.00 hours | |
| Target version: | Deuxième Itération 2019 | |||
| Remaining (hours) | 0.0 |
History
#1 Updated by Loic LUCOTTE over 3 years ago
- Status changed from New to In Progress
#2 Updated by Loic LUCOTTE over 3 years ago
- Status changed from In Progress to Closed
- Remaining (hours) changed from 4.0 to 0.0